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LY612568
Preliminary 0.2
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
REVISION HISTORY
Revision Rev. 0.1 Rev. 0.2 Description Preliminary Revised Test Condition of ISB1/IDR Revised VTERM to VT1 and VT2 Revised FEATURES & ORDERING INFORMATION Lead free and green package available to Green package available Added packing type in ORDERING INFORMATION Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS Revised PACKAGE OUTLINE DIMENSION Issue Date Dec.6.2006 Aug.26.2009
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 0
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LY612568
Preliminary 0.2
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
GENERAL DESCRIPTION
The LY612568 is a 2,097,152-bit low power CMOS static random access memory organized as 262,144 words by 8 bits. It is fabricated using very high performance, high reliability CMOS technology. Its standby current is stable within the range of operating temperature. The LY612568 is well designed for low power application, and particularly well suited for battery back-up nonvolatile memory application. The LY612568 operates from a single power supply of 5V and all inputs and outputs are fully TTL compatible
FEATURES
Fast access time : 15/20/25ns Low power consumption: Operating current: 100/80/75mA (TYP.) Standby current: 100A (TYP.) Single 5V power supply All inputs and outputs TTL compatible Fully static operation Tri-state output Data retention voltage : 2.0V (MIN.) Green package available Package : 44-pin 400 mil TSOP-II
PRODUCT FAMILY
Product Family LY612568 LY612568(E) LY612568(I) Operating Temperature 0 ~ 70 -20 ~ 80 -40 ~ 85 Vcc Range 4.5 ~ 5.5V 4.5 ~ 5.5V 4.5 ~ 5.5V Speed 15/20/25ns 15/20/25ns 15/20/25ns Power Dissipation Standby(ISB1,TYP.) Operating(Icc,TYP.) 100A 100/80/75mA 100A 100/80/75mA 100A 100/80/75mA
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
SYMBOL DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Inputs Write Enable Input Output Enable Input Power Supply Ground No Connection
Vcc Vss
A0 - A17 DQ0 - DQ7
DECODER 256Kx8 MEMORY ARRAY
CE# WE# OE# VCC VSS NC
A0-A17
DQ0-DQ7
I/O DATA CIRCUIT
COLUMN I/O
CE# WE# OE#
CONTROL CIRCUIT
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 1
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LY612568
Preliminary 0.2
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
PIN CONFIGURATION
NC NC A4 A3 A2 A1 A0 CE# DQ0 DQ1 Vcc Vss DQ2 DQ3 WE# A17 A16 A15 A14 A13 NC NC
1 2 3 4 5 6 7 8
44 43 42 41 40 39 38 37
NC NC NC A5 A6 A7 A8 OE# DQ7 DQ6 Vss Vcc DQ5 DQ4 A9 A10 A11 A12 NC NC NC NC
LY612568
9 10 11 12 13 14 15 16 17 18 19 20 21 22
36 35 34 33 32 31 30 29 28 27 26 25 24 23
TSOP-II
ABSOLUTE MAXIMUN RATINGS*
PARAMETER Voltage on VCC relative to VSS Voltage on any other pin relative to VSS Operating Temperature Storage Temperature Power Dissipation DC Output Current SYMBOL VT1 VT2 TA TSTG PD IOUT RATING -0.5 to 6.5 -0.5 to VCC+0.5 0 to 70(C grade) -20 to 80(E grade) -40 to 85(I grade) -65 to 150 1 50 UNIT V V W mA
*Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 2
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LY612568
Preliminary 0.2
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
TRUTH TABLE
MODE Standby Output Disable Read Write
Note:
CE# H L L L
OE# X H L X
WE# X H H L
I/O OPERATION High-Z High-Z DOUT DIN
SUPPLY CURRENT ISB1 ICC ICC ICC
H = VIH, L = VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
SYMBOL TEST CONDITION PARAMETER Supply Voltage VCC *1 Input High Voltage VIH *2 Input Low Voltage VIL Input Leakage Current ILI VCC VIN VSS Output Leakage VCC VOUT VSS, ILO Current Output Disabled Output High Voltage VOH IOH = -4mA Output Low Voltage VOL IOL = 8mA -15 Cycle time = Min. Average Operating ICC CE# = VIL , II/O = 0mA -20 Power supply Current Other pins at VIH or VIL -25 Standby Power CE# VCC - 0.2V ISB1 Supply Current Other pins at 0.2V or VCC-0.2V
Notes: 1. VIH(max) = VCC + 3.0V for pulse width less than 10ns. 2. VIL(min) = VSS - 3.0V for pulse width less than 10ns. 3. Over/Undershoot specifications are characterized, not 100% tested. 4. Typical values are included for reference only and are not guaranteed or tested. Typical valued are measured at VCC = VCC(TYP.) and TA = 25 5. 1mA for special request
MIN. 4.5 2.2 - 0.3 -1 -1 2.4 -
TYP. 5.0 -
*4
MAX. 5.5 VCC+0.3 0.8 1 1 0.4 140 110 100 3*
5
UNIT V V V A A V V mA mA mA mA
100 80 75 0.1
CAPACITANCE (TA = 25, f = 1.0MHz)
PARAMETER Input Capacitance Input/Output Capacitance SYMBOL CIN CI/O MIN.
-
MAX 8 10
UNIT pF pF
Note : These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 3
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LY612568
Preliminary 0.2
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Levels Output Load 0.2V to VCC - 0.2V 3ns 1.5V CL = 30pF + 1TTL, IOH/IOL = -8mA/16mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE PARAMETER Read Cycle Time Address Access Time Chip Enable Access Time Output Enable Access Time Chip Enable to Output in Low-Z Output Enable to Output in Low-Z Chip Disable to Output in High-Z Output Disable to Output in High-Z Output Hold from Address Change (2) WRITE CYCLE PARAMETER Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-up Time Write Pulse Width Write Recovery Time Data to Write Time Overlap Data Hold from End of Write Time Output Active from End of Write Write to Output in High-Z SYM. tRC tAA tACE tOE tCLZ* tOLZ* tCHZ* tOHZ* tOH LY612568-15 MIN. MAX. 15 15 15 7 4 0 7 7 3 LY612568-20 MIN. MAX. 20 20 20 8 4 0 8 8 3 LY612568-25 MIN. MAX. 25 25 25 9 4 0 9 9 3 UNIT ns ns ns ns ns ns ns ns ns
SYM. tWC tAW tCW tAS tWP tWR tDW tDH tOW* tWHZ*
LY612568-15 MIN. MAX. 15 12 12 0 10 0 8 0 4 8
LY612568-20 MIN. MAX. 20 16 16 0 11 0 9 0 5 9
LY612568-25 MIN. MAX. 25 20 20 0 12 0 10 0 6 10
UNIT ns ns ns ns ns ns ns ns ns ns
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 4
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LY612568
Preliminary 0.2
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC Address tAA Dout Previous Data Valid tOH Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
tRC Address tAA CE# tACE OE# tOE tOLZ tCLZ Dout High-Z tOH tOHZ tCHZ Data Valid High-Z
Notes : 1.WE# is high for read cycle. 2.Device is continuously selected OE# = low, CE# = low. 3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter. 4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured 500mV from steady state. 5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 5
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LY612568
Preliminary 0.2
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC Address tAW CE# tCW tAS WE# tWHZ Dout (4) High-Z tDW Din tDH TOW (4) tWP tWR
Data Valid
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)
tWC Address tAW CE# tAS tCW tWP WE# tWHZ Dout (4) High-Z tDW Din tDH tWR
Data Valid
Notes : 1.WE#, CE# must be high during all address transitions. 2.A write occurs during the overlap of a low CE#, low WE#. 3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be placed on the bus. 4.During this period, I/O pins are in the output state, and input signals must not be applied. 5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state. 6.tOW and tWHZ are specified with CL = 5pF. Transition is measured 500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 6
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LY612568
Preliminary 0.2
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
DATA RETENTION CHARACTERISTICS
PARAMETER VCC for Data Retention Data Retention Current Chip Disable to Data Retention Time Recovery Time tRC* = Read Cycle Time SYMBOL TEST CONDITION VDR CE# VCC - 0.2V VCC = 2.0V IDR CE# VCC - 0.2V Others at 0.2V or VCC-0.2V See Data Retention tCDR Waveforms (below) tR MIN. 2.0 0 tRC* TYP. 0.05 MAX. 5.5 2 UNIT V mA ns ns
DATA RETENTION WAVEFORM
VDR 2.0V Vcc Vcc(min.) tCDR CE# VIH CE# Vcc-0.2V Vcc(min.) tR VIH
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 7
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LY612568
Preliminary 0.2
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
PACKAGE OUTLINE DIMENSION
44-pin 400mil TSOP- Package Outline Dimension
SYMBOLS A A1 A2 b c D E E1 e L ZD y
DIMENSIONS IN MILLMETERS MIN. NOM. MAX. 1.20 0.05 0.10 0.15 0.95 1.00 1.05 0.30 0.45 0.12 0.21 18.212 18.415 18.618 11.506 11.760 12.014 9.957 10.160 10.363 0.800 0.40 0.50 0.60 0.805 0.076 o o o 3 6 0
DIMENSIONS IN MILS MIN. NOM. MAX. 47.2 2.0 3.9 5.9 37.4 39.4 41.3 11.8 17.7 4.7 8.3 717 725 733 453 463 473 392 400 408 31.5 15.7 19.7 23.6 31.7 3 o o o 0 3 6
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 8
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LY612568
Preliminary 0.2
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
ORDERING INFORMATION
LY612568 U V - WW Y Z
Z : Packing Type Blank : Tube or Tray T : Tape Reel Y : Temperature Range Blank : (Commercial) 0C ~ 70C E : (Extended) -20C ~ +80C I : (Industrial) -40C ~ +85C WW : Access Time(Speed) V : Lead Information L : Lead Free U : Package Type M : 44-pin 400 mil TSOP-II
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 9
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LY612568
Preliminary 0.2
5V 256K X 8 BIT HIGH SPEED CMOS SRAM
THIS PAGE IS LEFT BLANK INTENTIONALLY.
Lyontek Inc. reserves the rights to change the specifications and products without notice. 5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan. TEL: 886-3-6668838 FAX: 886-3-6668836 10

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